DAMASCENE REPLACEMENT METAL GATE PROCESS WITH CONTROLLED GATE PROFILE AND LENGTH USING Si1-xGex AS SACRIFICIAL MATERIAL

ABSTRACT

A method of forming a metal gate in a wafer. PolySi 1-x Ge x  and polysilicon are used to form a tapered groove. Gate oxide, PolySi 1-x Ge x , and polysilicon is deposited on a wafer. A resist pattern is formed. A portion of the polysilicon, PolySi 1-x Ge x , and gate oxide is removed to provide a tapered profile. The resist is removed; a dielectric liner is deposited, and then at least a portion of the dielectric liner is removed, thereby exposing the polysilicon and leaving the dielectric liner in contact with the polysilicon, PolySi 1-x Ge x , and gate oxide. A dielectric is deposited, and a portion is removed thereby exposing the polysilicon. The polysilicon, PolySi 1-x Ge x , and gate oxide is removed from inside the dielectric liner, thereby leaving a tapered gate groove. Metal is then deposited in the groove.

RELATED APPLICATION (PRIORITY CLAIM)

This patent application is a divisional of U.S. patent application Ser.No. 10/889,901, filed on Jul. 13, 2004.

BACKGROUND

The present invention generally relates to damascene metal gateprocesses, and more specifically relates to a damascene metal gateprocess which uses Si_(1-x)Ge_(x) as a sacrificial member.

The aggressive scaling of metal oxide semiconductor (MOS) devices isquickly reaching the fundamental limits of SiO₂ as the gate dielectric.Scaling requirements can no longer be achieved with SiO₂ ornitrided-SiO₂ gate dielectrics due to the presence of excessive leakagecurrents arising from direct tunneling and the lack of manufacturabilityof sub-1 nm oxides. Moreover, poly-Si depletion and threshold voltageshifts due to boron penetration into the channel region severely degradedevice performance. Replacement of SiO₂-based gate dielectrics with ahigh dielectric constant (high-k) material provides a means to addressscaling issues. A high-k material allows for a physically thicker filmto meet the required gate capacitance, while reducing the leakagecurrent due to direct tunneling and improving manufacturability.

The issue of poly-Si depletion is still not overcome when using a high-kmaterial, since the 3-6A contribution to EOT due to poly-Si depletion isstill about 30-50% of the target EOT. As a result, the semiconductorindustry began investigating metal gate electrodes. Replacement ofpoly-Si with a metal electrode solves both the boron penetration andpoly-Si depletion issues. Moreover, the introduction of metal gates canprolong the use of SiO₂ for one or two technology generations for highperformance applications before requiring a switch to high-kdielectrics.

A major challenge to the introduction of metal electrodes is addressingthe issue of how to integrate the material into conventional transistorprocessing. In the case of CMOS and partially depleted SOI, two metaltypes will be needed, one with an n-type work function and one with ap-type work function. In the case of fully depleted SOI, a single metalwith a mid-gap work function can be used. Whether one type or two typesof metals are used, the integration question is still open. Manycandidate metals will not sustain a standard source/drain activationanneal due to either reaction with the gate dielectric or the lowmelting temperature of many metal materials. In order to increase thenumber of candidate metal materials, a replacement gate approach is veryappealing.

A replacement gate approach using a damascene scheme has been proposedpreviously, and is illustrated in FIGS. 1-5. As shown in FIG. 1, theapproach provides that polysilicon dummy gates 10 are fabricated usingstandard polysilicon gate CMOS process flow until the formationsource/drain (wherein the source is identified with reference numeral 12in FIG. 1 and the drain is identified with reference numeral 14 in FIG.1). Then, as shown in FIG. 2, pre-metal dielectric 16 is deposited onthe silicon wafer 18 and a dielectric CMP planarization process isperformed (as represented by arrows 20 in FIG. 2). The dummy polysilicon10 and gate oxide 22 are then removed by reactive ion etching (RIE)and/or wet chemical etching to form a gate groove 24 as shown in FIG. 3.As shown in FIG. 4, a new gate dielectric (SiO₂ or high-k dielectric) 26and metal gate 28 are grown and/or deposited on the wafer and, as shownin FIG. 5, a CMP step is performed (represented by arrows 30 in FIG. 5)to finally form the metal gate electrode 32. The main advantage of usinga damascene process is that it avoids the thermal and plasma damages tothe gate dielectric and metal electrode stacks during source/drain ionimplantation, activation annealing and gate RIE.

A major problem of the existing damascene replacement scheme for metalgates is associated with the dummy polysilicon profile. The standardCMOS polysilicon gate etch process in general can only achieve a taperedpolysilicon profile 40 with an angle of 87-89 degrees as shown in FIG. 6(i.e., the polysilicon will have an actual profile such as that which isshown in FIG. 6, as opposed to the theoretical profile depicted inFIG. 1) causing a re-entrant gate groove 42 as shown in FIG. 7 (i.e.,the gate groove will have an actual profile such as that which is shownin FIG. 7 as opposed to the theoretical profile depicted in FIG. 3).This leads to the following disadvantages of the scheme:

-   -   (a). Dummy polysilicon residue 44 as illustrated in FIG. 7:        Incomplete removal of dummy polysilicon the sidewall, especially        when a RIE is used to remove the dummy polysilicon.    -   (b). Incomplete dummy gate dielectric removal or undercut        beneath residue polysilicon.    -   (c). Difficulty of groove filling with new gate dielectric and        metal electrode. Voids could be formed due to the lack of gap        filling capability for the gate dielectric and metal electrode        inside these narrow and high aspect ratio grooves, which will in        turn limit the scalability of this scheme for the future        technology nodes.

OBJECTS AND SUMMARY

An object of an embodiment of the present invention is to provide amethod of forming a metal gate in a wafer which does not result inpolysilicon residue being left in a groove before the groove is filledwith metal.

Another object of an embodiment of the present invention is to provide amethod of forming a metal gate in a wafer wherein a tapered groove isformed that tapers from an opening at its top to the bottom of thegroove.

Yet another object of an embodiment of the present invention is toprovide a metal gate in a wafer, where there is a groove which has atapered profile which converges from an opening to a base, and there ismetal in the groove, thereby providing the metal gate.

Briefly, and in accordance with at least one of the foregoing objects,an embodiment of the present invention provides a method of forming ametal gate in a wafer wherein PolySi_(1-x)Ge_(x) is used as asacrificial member to form a tapered groove. Specifically, gate oxide,PolySi_(1-x)Ge_(x), and polysilicon is deposited on a wafer. A resistpattern is formed. A portion of the polysilicon, PolySi_(1-x)Ge_(x), andgate oxide is removed to provide a tapered profile. The resist isremoved; a dielectric liner is deposited, and then at least a portion ofthe dielectric liner is removed, thereby exposing the polysilicon andleaving the dielectric liner in contact with the polysilicon,PolySi_(1-x)Ge_(x), and gate oxide. A dielectric is deposited, and aportion is removed thereby exposing the polysilicon. The polysilicon,PolySi_(1-x)Ge_(x), and gate oxide is removed from inside the dielectricliner, thereby leaving a tapered gate groove. Metal is then deposited inthe groove.

BRIEF DESCRIPTION OF THE DRAWINGS

The organization and manner of the structure and operation of theinvention, together with further objects and advantages thereof, maybest be understood by reference to the following description, taken inconnection with the accompanying drawings, wherein:

FIGS. 1-7 are views which relate to a prior art damascene metal gateprocess;

FIG. 8 is a flow chart which illustrates a damascene metal gate processwhich is in accordance with an embodiment of the present invention; and

FIGS. 9-14 are views which relate to the process illustrated in FIG. 8.

DESCRIPTION

While the invention may be susceptible to embodiment in different forms,there are shown in the drawings, and herein will be described in detail,specific embodiments of the invention. The present disclosure is to beconsidered an example of the principles of the invention, and is notintended to limit the invention to that which is illustrated anddescribed herein.

The present invention aims to improve the dummy gate profile, eliminatethe re-entrant profile of gate grooves, and extend the damascenereplacement scheme to future technology nodes.

Instead of using pure polysilicon as dummy gate, the new method involvesthe use of a polysilicon/PolySi_(1-x)Ge_(x) film stacks as a dummy gate.FIG. 8 illustrates the process on a step-and-step basis, and theprogression of FIGS. 9 through 14 show the process being performed.Initially, as shown in FIG. 9, a gate oxide 50 is deposited oil asilicon wafer 52, and then polysilicon 54 and PolySi_(1-x)Ge_(x) 56films are deposited. The Ge composition in the PolySi_(1-x)Ge_(x) may beanywhere from 15 to 50 percent depending on the application. Then, aresist 58 is patterned on the polysilicon 54. The wafer 52 is thenprocessed through dummy gate etching (i.e., portions of the polysilicon54, PolySi_(1-x)Ge_(x) 56, and gate oxide 50 are etched away) and theresist 58 is stripped and cleaned, thereby providing that which is shownin FIG. 10. After the desired degree of re-entrant profile has beenachieved, a dielectric liner 60 (e.g. oxide or nitride, such as SiO2,Si3N4, or some other High-K dielectric) is deposited as shown in FIG.11, which is followed by an anisotropic plasma etch to remove thedielectric on top of the polysilicon and active areas, thereby leavingthe structure as shown in FIG. 12, wherein the top 62 of the polysilicon54 is exposed, but the dielectric liner 60 is left intact along the sidewall 64 of the polysilicon 54, PolySi_(1-x)Ge_(x) 56, and gate oxide 50.The dielectric liner 60 on the side wall 64 prevents Si_(1-x)Ge_(x) 56from further oxidizing and wet etching, thus preserving the dummy gateprofile and gate electrode dimension throughout the subsequentprocesses. Subsequently, the following steps are performed: LDDimplantation and anneal, LTO oxide and Si3N4 deposition and etch to formspacer, SD implantation and anneal, salicide formation; depositing apre-metal dielectric (such as a standard ILD oxide layer such as HDPoxide, FSG, or BPSG) on the polysilicon; and CMP removing a portion ofthe dielectric thereby exposing the polysilicon. Subsequently, thepolysilicon 54, PolySi_(1-x)Ge_(x) 56, and gate oxide 50 are removedfrom inside the dielectric liner 60, thereby leaving a tapered gategroove 66 as shown in FIG. 13. As shown, the groove 66 is wider at anopening 68 at its top 70 than at its bottom 72, proximate the siliconwafer 52. Then, a gate dielectric 74 such as SiO2, SiON, or a high-Kdielectric is deposited. Finally, metal 76 is deposited into the groove66, and is etched to provide the final structure shown in FIG. 14.

By manipulating the Ge composition in the PolySi_(1-x)Ge_(x), the plasmaetching chemistries of Si_(1-x)Ge_(x), oxidation, and oxide wet etching,a re-entrant PolySi_(1-x)Ge_(x) profile can be achieved (as shown inFIGS. 10-12), wherein the PolySi_(1-x)Ge_(x) 56 is wider at its top 78,proximate the polysilicon 54, than it is at its bottom 80, proximate thegate oxide 50. This re-entrant dummy gate profile then yields a taperedgate groove 66 as shown in FIG. 13 after processing through source/drainformation and dummy gate removal. This tapered profile thus can achievemuch smaller gate length, improve gate dielectric and metal gateelectrode gap fill.

The capability of the manipulation of Si_(1-x)Ge_(x) resides in the factthat the Si₁ Ge_(x) has higher oxidation rate than silicon, andgermanium oxide is a volatile compound. The present method involves theuse of F/Cl2 based chemistries for plasma etching of polysilicon portionas well as the use of Cl2/HBr/O2 based chemistries for etching thePolySi_(1-x)Ge_(x) portion of the film stack. The inclusion of O2 in theetch chemistry results in a diminished Si_(1-x)Ge_(x) dimension withrespect to the polysilicon (L_(siGe)/L_(Si)=0.8 with L_(siGe) and L_(si)being the dimensions of the PolySi_(1-x)Ge_(x) and silicon,respectively).

The profile of Si_(1-x)Ge_(x) can be further manipulated by using a wetchemistry (such as SCl) that includes an oxidizing agent (such as H2O2or O3) and an acid or base, such as NH4OH, to dissolve the oxidizedsurface. The film thickness of polysilicon/Poly Si_(1-x)Ge_(x), and thecomposition of Ge in the Si_(1-x)Ge_(x) alloy can also be adjusted tofit the requirements of the final profile and CDs.

Hence, the process has the following features:

-   -   (a). Deposition of polysilicon/Poly Si_(1-x)Ge_(x) film stacks        as damascene replacement dummy gate materials.    -   (b). Manipulation of the plasma etch chemistries, Ge        composition, film stack thickness, and wet clean chemistries to        achieve a desired re-entrant dummy gate profile.    -   (c). Dielectric liner deposition and plasma etching to provide a        dielectric sidewall for preserving the gate groove profile.    -   (d). A unique gate profile.    -   (e). Scalability: can be used to achieve small gate length        without the need of small line print.    -   (f). Prevention of the incomplete polysilicon strip and undercut        after dummy gate dielectric removal.    -   (g). Improved subsequent new gate dielectric and metal gate        electrode gap fill capability.

While embodiments of the present invention are shown and described, itis envisioned that those skilled in the art may devise variousmodifications of the present invention without departing from the spiritand scope of the appended claims.

1. A metal gate in a wafer comprising: a groove which has a taperedprofile which converges from an opening to a base; metal in the groove,thereby providing said metal gate.
 2. A metal gate as recited in claim1, further comprising a dielectric liner on a side of said groove.
 3. Ametal gate as recited in claim 2, further comprising a dielectric layer,said dielectric liner being disposed between said dielectric layer andsaid metal.